Introduction
In this section we will cover some of the basic instructions
used in PLC programming. These instructions are some of the most used
instructions in PLC programming. Once we explain in detail the instructions then
we will have a look at how we can implement and used those instructions in real
life application.
Definition
The following is a list of the basic instructions in SLC
500:
- XIC - Examine if Closed
- XIO - Examine if Open
- OTE - Output Energize
- OTL - Output Latch
- OTU- Output Unlatch
- OSR - One-Shot Rising
XIC Examine if Closed
Symbol
Definition
Examines a bit for an On condition
Use the XIC instruction in your ladder logic to determine if
a bit is ON.
0 = False
1 = True
Devices
Start/Stop push buttons
Selectors
Limit switch
Proximity switch
Light
Internal bit
Symbol
Definition
Examines a bit for an off condition.
Use an XIO instruction in your ladder logic to determine if
a bit if off.
1 = True
0 = False
Devices
Start/Stop push buttons
Selectors
Limit switch
Proximity switch
Light
Internal bit
Symbol
Definition
Turns a bit on or off
Use OTE instruction in your ladder logic to turn on a bit
when rung condition is evaluated as true.
Devices
Light
Motor run signal
Internal bits
Usually we latch a signal with a condition and then unlatch
it when a different condition becomes true. Most of time the Latch / Unlatch go
together.
Symbol
Definition
Turns a bit on when the rung is executed, and this bit
retains its state when the rung is not executed or a power cycle power occurs.
OTL is a retentive output instruction. OTL can only turn on
a bit. This instruction is usually used with OTU with both OTL and OTU
addressing the same bit.
Ladder logic can examine a bit controlled by OTL as often as
necessary.
When you assign an address to the OTL instruction that
corresponds to the address of a physical output, the output device wired to the
screw terminal is energized when the bit is set. When rung conditions become
false, the bit remains set and the corresponding output device remains
energized.
Actuating the latch input turns the function on or causes it
to change state. The function then stays on even if the latch input is turned
off. To turn the function off, another input must unlatch which turns the
function off.
Symbol
Definition
Turns a bit off when the rung is executed, and this bit
retains its state when the rung is not executed or when power cycle occurs.
OTU is a retentive output instruction. OTU can only turn off
a bit. This instruction is usually used with OTL with both OTL and OTU
addressing the same bit.
Ladder logic can examine a bit controlled by OTU as often as
necessary.
When you assign an address to the OTU instruction that
corresponds to the address of a physical output, the output device wired to the
screw terminal is de-energized when the bit is cleared.
The unlatch instruction tells the controller to turn off the
addressed bit. Thereafter, the bit remains off, regardless of the rung
condition, until it is turned on.
Symbol
Definition
Triggers a one-time event.
The OSR instruction is a retentive input instruction that
triggers an event to occur only one time. Use the OSR instruction when an event
must start based on change of state of the rung from false to true.
When the input instruction goes from false to true, the OSR
instruction conditions the rung so that the output goes true for one scan. The
output goes false and remains false for successive scans until the input makes
another false to true transition.
Scenario
Use the XIC instruction in your ladder logic to determine if
a bit is ON.
Use an XIO instruction in your ladder logic to determine if
a bit if off.
Use OTE instruction in your ladder logic to turn on a bit
when rung condition is evaluated as true.
Example 1
Let’s construction a simple circuit with one switch as a
contact and one output as a coil. When the switch is on the light will go on
and when the switch is off the light will turn off.
Input / Output
Switch I: 1.0/0
Light O: 2.0/0
Ladder Logic Solution
When the switch is on the input Address: I: 1.0/0 will be on
and hence the rung will be energized hence the outputs on address O: 2.0/0 will
be energize and the light will go on.
When the switch is off the rung will be de-energized and the
light will go off.
Example 2
Let’s build an alarm system. Let's assume that we have 3
signals (Inputs) that we get from the field that warn us about some kind of
fire danger.
Any 1 signal, turn the warning light on;
Any 2 signals will sound the siren.
All 3 signals, will start the water spray system
Input / Output
Alarm 1 I:1.0/7
Alarm 2 I:1.0/8
Alarm 3 I1.0/9
Siren O:2.0/7
Alarm Light O:2.0/8
Spray System O:2.0/9
Ladder Logic Solution
We put all the alarm signals in parallel. This is equivalent
to an or statement. This means that when either Alarm1 or Alarm2 or Alarm3
becomes on the rung will be energized and hence the Fire light will be turned
on. This does not take care of the count of the alarms. It only look at
whatever alarm is on.
Here we put every possible combination of 2 alarms in a
separate line. This is equivalent to an end statement. (Alarm1 and Alarm2) or
(Alarm1 and Alarm3) or This takes care of 2 alarms at a time in which case if
any of these combinations becomes true the Fire siren will go on.
As you can see the 2 alarms are in series. This is
equivalent to an and statement. Which is (Alarm1 and Alarm2 and Alarm3) if and
only if alarm1 and alarm2 and alarm3 are on (3 of them) it is only then that
the fire spray will be turned on.
Note
· Contacts in parallel are equivalent to an OR statement
· Contacts in series are equivalent to an AND statement
Basic Motors
This section covers some of the basic Start / Stop Motor
logic. The purpose of this section is to give PLC programmers a sense of some
of the basics in Motor control in ladder logic. We have included some of the
most used controls. More advanced section for motor section is available later
on in the training section.
Example 1
Assume we have a motor that could be started and stopped
from 3 different places. What this mean is that we have 3 sets of Start/Stop
buttons that can start and stop the motor.
Solution:
Rung 0: Here we have put Star1/Start2 /Start3 in parallel
and then pass it thru a one shot. We are assuming that the start button could
also have a maintained (1) signal as well as momentary (2) signal. So to cover
both cases, this will prevent the motor from starting automatically after any
of the 3 stop buttons is pressed. It is just a precaution and better as far as
security is concerned.
Rung 1 : Here we have the stop buttons in series, since
pressing any of the buttons should stop the motor and will disallow any of the
start button to pass thru.
Note
Maintained signal is a signal that stays on when a push
button is pressed. Typically a selector has a maintained signal. Some type of
push buttons has a maintained signal. When you press on lets say on a start
push button, the start bit will stay on until the stop button is press.
A momentary signals is a signal that will go on for as long
as the operator pushes the button. When the operator release the button the
signal will go off. That is why most of the time we use the OSR instruction to
lock on the signal.
Ladder Logic Counters
In this section we will cover the count up count down and
reset instruction. Counters are very essential in ladder logic programming.
Counters are used to index, increment or decrement values.
Definition
The following is a list of counter instructions in SLC 500:
- CTU - Count Up
- CTD - Count Down
- RES - Reset
- CTU Count UP
Symbol
Definition
Increments the accumulated value at each false to true
transition and retains the accumulated value when the instruction goes false or
when power cycle occurs.
The CTU is an instruction that counts false to true
transition. When this transition happens the accumulated value is incremented
by one count.
A CTU accumulation is reset by the RES instruction.
If the accumulation value is over the maximum range then the
overflow (OV) bit will be true.
Each counter address is made of a 3-word element.
Word 1 is the control word
Bit 0-7: Internal Use
Bit 10: UA - Update accumulation value.
Bit 11: UN - Underflow bit.
Bit 12: OV - Overflow bit.
Bit 13: DN - Done
Bit 14: CD - Count down is enabled.
Bit 15: CU - Count up is enabled.
Word 2 stores the preset value. (PRE)
Specifies the value, which the counter must reach before the
controller sets the done bit. When the accumulator value becomes equal to or
greater than the preset value, the done status bit is set. You can use this bit
to control an output device.
Preset value is from -32,768 to 32,767
If a timer-preset value is negative an error will occur.
Word 3 stores the accumulated value. (ACC)
This is the number of times of false to true transitions
that have occurred since the counter was last rest.
Symbol
Definition
Decrements the accumulate value at each false to true
transition and retains the accumulated value when the instruction goes false or
when power cycle occurs.
The CTD is an instruction that counts false to true
transition. When this transition happen the accumulated value is decrements by
one count.
A CTD accumulation is reset by the RES instruction.
If the accumulation value is below the minimum range then
the underflow (UN) bit will be true.
· Each counter address is made of a 3-word element.
Word 1 is the control word
- Bit 0-7: Internal Use
- Bit 10: UA - Update accumulation value.
- Bit 11: UN - Underflow bit.
- Bit 12: OV - Overflow bit.
- Bit 13: DN - Done
- Bit 14: CD - Count down is enabled.
- Bit 15: CU - Count up is enabled.
Word 2 stores the preset value. (PRE)
Specifies the value, which the counter must reach before the
controller sets the done bit. When the accumulator value becomes equal to or
greater than the preset value, the done status bit is set. You can use this bit
to control an output device.
Preset value is from -32,768 to 32,767
If a timer-preset value is negative an error will occur.
· Word 3 stores the accumulated value. (ACC)
Symbol
Definition
Resets the accumulated value and status bit of a timer or
counter.
Use a RES instruction to reset timers or counters. When the
RES instruction is enabled, it resets the Timer On Delay, Retentive Timer, and
Counter Up, Counter Down instruction having the same address as the RES
instruction.
Ladder Logic Timers
SLC 500 Training: In this section we will cover timers used
in ladder logic programming. Timers are very important in ladder logic
programming. Timers gives the precision in time. Timer on delay starts timing
when instruction is true. Timers are used to track time when instruction are on
or off. They could also keep track on a retentive base.
Definition
The following is a list of timer instructions in SLC 500:
- TON - Timer On Delay
- TOF - Timer Off Delay
- RTO - Retentive Timer
Symbol
Definition
Count time base intervals when the instruction is true.
The Timer On Delay instruction begins to count time base
intervals when rung conditions become true. As long as rung conditions remain
true, the timer adjust its accumulated value (ACC) each evaluation until it
reaches the preset value (PRE). The accumulated value is reset when rung
conditions go false, regardless of whether the timer has timed out.
Each Timer on Delay is made of a 3-word element.
Word 1 is the control word
- Bit 0-12: Internal Use
- Bit 13: Done (DN) this bit is on when the Accumulation value >= Preset Value
- Bit 14: Timer Timing (TT) this bit is on when the timer is timing
- Bit 15: Enabled (EN), this bit is on when the timer is energized.
Word 2 stores the preset value. (PRE)
The programmer specifies this value. When the accumulated
time reaches the preset value the controller sets the done bit. When the
accumulated value becomes equal to or greater than the preset value, the done
bit is set. Usually preset value is from 0 - 32,767
If a timer-preset value is negative an error will occur.
Word 3 stores the accumulated value. (ACC)
This is the time elapsed since the timer was last reset.
When enabled the timer updates this continually.
Time Base: is the timing update interval, this can vary from
0 - 1 second.
Symbol
Definition
Counts time base intervals when the instruction is false.
The Timer Off Delay instruction begins to count time base
intervals when the rung makes a true to false transition. As long as rung
conditions remain false, the timer increments its accumulated value (ACC each
scans until it reaches the preset value (PRE). The accumulated value is reset
when rung conditions go true regardless of whether the timer has timed out.
Each timer address is made of a 3-word element.
Word 1 is the control word
- Bit 0-12: Internal Use
- Bit 13: DN- Done
- Bit 14: TT - Timer Timing
- Bit 15: EN - Timer is enabled
Word 2 stores the preset value. (PRE)
Specifies the value, which the timer must reach before the
controller sets the done bit. When the accumulated value becomes equal to or
greater than the preset value, the done bit is se.
Preset value is from 0 - 32,767
If a timer-preset value is negative an error will occur.
Word 3 stores the accumulated value. (ACC)
This is the time elapsed since the timer was last reset.
When enabled the timer updates this continually.
Time Base: is the timing update interval, this can vary from
0 - 1 second.
Symbol
Definition
Counts time base intervals when the instruction is true and
retains the accumulated value when the instruction goes false or when power
cycle occurs.
The Retentive Timer instruction is a retentive instruction
that begins to count time base intervals when rung conditions become true.
The Retentive Timer instruction retains its accumulated
value when any of the following occurs:
Rung conditions become false.
Changing Processor mode from REM run /Test / program mode.
The processor loses power while battery back up is still
maintained.and a fault occurs.
Note:To reset the accumulated value in RTO, you must use a
reset instruction (RES) with the same address.
Each Retentive Timer is made of a 3-word element.
Word 1 is the control word
- Bit 0-12: Internal Use
- Bit 13: DN- Done
- Bit 14: TT - Timer Timing
- Bit 15: EN - Timer is enabled
Word 2 stores the preset value. (PRE)
Specifies the value, which the timer must reach before the
controller sets the done bit. When the accumulated value becomes equal to or
greater than the preset value, the done bit is se.
Preset value is from 0 - 32,767
If a timer-preset value is negative an error will occur.
Word 3 stores the accumulated value. (ACC)
This is the time elapsed since the timer was last reset.
When enabled the timer updates this continually.
Time Base: is the timing update interval, this can vary from
0 - 1 second
Arithmetic Instructions in Ladder Logic
Basic Ladder Logic instructions allow very simple logical
decisions. Arithmetic Ladder Logic instructions go beyond the simple true or
false operation to give the ability to more complex operations. It retrieves
one or more value, perform an operation and store the result in memory.
Status File
There is a very close relation between math instruction and
some of the control status bits. After a math instruction is executed, the
arithmetic status bits in the control status file are updated. Control status
file is the data file "S2 - Status".
S:0/0 Carry (C) Sets if carry is generated; otherwise it is
cleared.
S:0/1 Overflow (V) Indicates that the actual result of a
math instruction does not fit in the designated destination
S:0/2 Zero (Z) Indicates a 0 value after a math, move or a
logic instruction
S:0/3 Sign (S) Indicates a negative value after a math, move
or logic instruction.
S:5/0 Minor Error Minor error bit is set upon detection of a
mathematical overflow, or division by zero. This error can cause a CPU fault,
which could be avoided if the bit is unlatched before the END, TND, or REF
statement.
S:13S:14 Math register S:13 -Contains the least significant
word of the 32 bit values of MUL, DDV, FRD, and TODS:14 -Contains the Most
significant word of the 32 bit values of MUL, DDV, FRD and TOD
Definition
The following is a list of the comparison instructions in
SLC 500:
ADD - Adding
SUB - Subtract
MUL - Multiply
DIV - Division
DDV - Double Divide
Symbol
Definition
When rung conditions are true, this output instruction adds
Source A to Source B and stores the result at the destination address. Source A
and Source B can either be values or addresses that contain values, however
Source A and Source B cannot both be constants.
Carry (C), Sets if carry is generated; otherwise resets.
Cleared For floating value
Overflow (V), Sets if underflow; otherwise resets
Zero (Z), Sets if the result is Zero; otherwise resets;
Sign (S), Sets if result is negative; otherwise resets;
Symbol
Definition
When rung conditions are true, the SUB output instruction
subtracts Source B from Source A and stores the result in the destination.
Source A and Source B can either be values or addresses that contain values,
however Source A and Source B cannot both be constants.
Carry (C), Sets if borrow is generated; otherwise resets.
Cleared For floating value
Overflow (V), Sets if underflow; otherwise resets
Zero (Z), Sets if the result is Zero; otherwise resets;
Sign (S), Sets if result is negative; otherwise resets;
Symbol
Definition
Use the MUL instruction to multiply one value (source A) by
another (source B) and place the result in the destination. Source A and Source
B can either be constant values or addresses that contain values, however
Source A and Source B cannot both be constants.
The math register contains the 32-bit signed integer result
of the multiply operation. This result is valid at overflow.
Carry (C), Always reset
Overflow (V), Sets if overflow; otherwise resets
Zero (Z), Sets if the result is Zero; otherwise resets;
Sign (S), Sets if result is negative; otherwise resets;
Symbol
Definition
When rung condition is true, this output instruction divides
Source A by Source B and stores the result in the destination and the math
register. The value stored in the destination is rounded. The value stored in
the math register consists of the unrounded quotient (placed in the most
significant word) and the remainder (placed in the least significant word).
Source A and Source B can either be constant values or
addresses that contain values, however Source and Source B cannot both be
constants.
Carry (C), Sets if carry is generated; otherwise resets.
Cleared For floating value
Overflow (V), Sets if division by zero or overflow;
otherwise resets
Zero (Z), Sets if the result is Zero; otherwise resets,
undefined if overflow
Sign (S), Sets if result is negative; otherwise resets;
undefined if overflow.
Symbol
Definition
When rung conditions are true, this output instruction
divides the contents of the math register (S:13 and S:14), containing 32 bits
of data, by the source (16 bits of data) and stores the result in the
destination and the math register.
The math register initially contains the dividend of the DDV
operation. Upon execution the unrounded quotient is placed in the most
significant word of the math register. The remainder is placed in the least
significant word of the math register.
Carry (C), Sets if carry is generated; otherwise resets.
Cleared For floating value
Overflow (V), Sets if division by zero or result > 32 767
or < 32768; otherwise resets
Zero (Z), Sets if the result is Zero; otherwise resets;
Sign (S), Sets if result is negative; otherwise resets;
undefined if overflow.
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